FIG. 1 (Prior Art) is a diagram of a circuit 1 that drives a motor 2. The circuit drives the motor by driving a current into a selected one of the motor terminals 3-5 of the motor and out of another selected one of the terminals 3-5 of the motor so that the current flows through a selected pair of the three motor windings 6-8. Integrated circuit 9 has high-side drivers 10-12 and low-side drivers 13-15 organized in three pairs. The high-side and low-side drivers control associated external discrete N-channel field effect transistors (NFETs) 16-21. By controlling which ones of the external discrete NFETs are conductive and nonconductive, currents can be made to flow through selected ones of the windings of the motor so that the motor is driven as desired.
For example, in a first period of time, a current can be driven into motor terminal 3 and drawn out of motor terminal 4. To do this, high-side driver 10 turns on external discrete NFET 16 via terminal 22. Low-side driver 13 controls external discrete NFET 17 to be off via terminal 23. Similarly, low-side driver 15 controls external discrete NFET 21 to be on via terminal 24, and high-side driver 12 controls external discrete NFET 20 to be off via terminal 25. High-side driver 11 controls NFET 18 to be off and low-side driver 14 controls NFET 19 to be off. A current therefore flows from VDC conductor 26, through conductive NFET 16, to node 27, into motor 2 via motor terminal 3, through winding 6, to center node 28, through winding 7 to motor terminal 4, and through conductive NFET 21 to ground conductor 29. After an amount of time, it may be desired to stop the flow of current into motor terminal 3. High-side driver 10 therefore turns external discrete NFET 16 off. Despite that fact that both NFETs 16 and 17 are controlled to be off, the energy stored in the inductance of winding 6 will attempt to draw current from node 27, and this will cause the voltage on node 27 to pulse negative.
Each of the high-side drivers is a complementary logic inverter structure that involves an N-channel pull-down transistor and a P-channel pull-up transistor. In the illustrated example, the pull-down transistor is an N-channel Lateral Double-diffused MOS (N-channel LDMOS) transistor. The pull-up transistor is a P-channel LDMOS transistor. For high-side driver 10, the drains of the two LDMOS transistors are coupled together and to terminal 22. The source of the n-channel pull-down LDMOS transistor is coupled to terminal 30.
FIG. 2 (Prior Art) is a simplified cross-sectional diagram of the n-channel LDMOS pulldown transistor 35 within high-side driver 10. The negative voltage spike on node 27 manifests itself a negative voltage spike on the drain electrode 31 of the transistor. This negative voltage spike can cause an inrush of current that flows from the P type substrate 32, into the N type well 33, and through the N+ type contact diffusion 34, and to the drain electrode 31.
FIG. 3 (Prior Art) is a waveform diagram that shows the voltage on drain electrode 31 relative to ground potential on the substrate 32. In the illustrated example, the pull-down transistor 35 of the high-side driver 10 actually failed due to the high current condition. The voltage on the drain exceeded −0.7 volts, and reached −5.0 volts. In other cases, the pull-down transistor 35 does not fail but nonetheless the large surge current is undesirable. The large surge current may, for example, cause the pull-down transistor 35 to latch up, or may cause another device on the integrated circuit 9 to latch up. The large surge current may stress the pull-down transistor 35 so that the device is damaged over time with repeated use.
Each of the external discrete NFETs has an associated diode that helps solve the negative pulse voltage problems. These diodes are labeled with reference numerals 36-41 in FIG. 1. Consider, for example, diode 37 of external discrete NFET 17. If the inductive load being driven attempts to draw current from node 27 when both NFETs 16 and 17 are off, and if as a result the voltage on node 27 starts to spike negative, then diode 37 is to become conductive when the voltage on node 27 reaches −0.7 volts. A current can then flow from the ground conductor 29, through the forward biased diode 37, and to node 27. The diode 37 is to clamp the voltage on node 27 from going more negative than the forward voltage drop of diode 37, thereby protecting the pulldown LDMOS transistor 35 in high-side driver 10 from the effects of large negative voltage spikes.